Lead STA Engineer

About the role

Envision Employment Solutions is recruiting a Lead STA Engineer for a partner IT services and IT consulting company. The role sits in the Semiconductor Engineering department and involves setting the timing methodology, guiding the team through timing closure and making the final timing signoff decision on chips.

Key responsibilities

• Lead full chip and block-level STA and timing signoff on advanced nodes (10nm and below)
• Define timing methodology, signoff criteria, corners and modes
• Own SI and noise analysis, OCV/AOCV/POCV strategy and signoff closure
• Drive ECO generation and implementation for timing and functional fixes
• Review and guide constraint quality across RTL, synthesis and PnR teams
• Mentor and lead a team of timing engineers
• Build and improve timing automation and reporting flows

Required profile

• 10+ years of physical design experience, with a strong focus on STA and timing signoff
• Proven experience leading timing closure on complex SoCs at 10nm or below
• Multiple successful tapeouts as timing owner
• Experience leading or mentoring engineers

Required skills

• Expert knowledge of PrimeTime and/or Tempus, including PTSI
• Deep understanding of SDC, multimode multicorner analysis and variation modelling
• Strong scripting in Tcl, Perl and Python