Senior Engineer, Design Verification Engineering

About the role

Analog Devices, a global semiconductor company, is hiring a Senior Engineer for its Design Verification team in New Cairo. The role covers both functional and formal verification of SoCs, working closely with designers and system engineers.

Key responsibilities

• Create, enhance and maintain SystemVerilog/UVM verification environments, checkers, scoreboards, assertions and functional coverage models
• Develop verification plans and metric-driven closure through code, functional and assertion coverage and regression analysis
• Build constrained-random and directed test scenarios covering functional, security and corner-case behavior
• Maintain and upgrade existing testbenches and write firmware-driven test cases (C) for embedded processor co-simulation
• Architect formal verification environments from scratch, including FPV wrappers, constraints and proof orchestration scripts
• Write SVA assertions for protocol compliance, data integrity, arbitration fairness and design intent
• Integrate AMBA AHB/APB protocol VIPs into formal and functional verification environments
• Develop formal coverage models and analyze proof convergence, unreachability and counterexamples
• Collaborate with designers and system engineers on cross-block verification and contribute to top-level SoC verification, including boot sequences, emulation support, firmware integration and post-silicon validation

Required profile

• Bachelor's or Master's degree in Electrical or Computer Engineering
• At least 3+ years of experience in design verification
• Hands-on experience building formal property verification environments from scratch
• Experience writing SVA for bus protocol verification (AMBA AHB/APB/AXI)
• Experience with C/C++ for firmware-level test development and scripting (Python, Tcl, shell)

Required skills

• Proficiency in SystemVerilog, SVA and UVM
• Functional coverage and constrained-random verification
• Common SoC interfaces: APB, AHB, AXI, QSPI, UART, DMA
• Preferred: commercial protocol VIPs (Cadence, Synopsys), ARM Cortex-M verification, non-volatile memory verification, Perforce/Git, emulation or FPGA prototyping

The role requires travel about 10% of the time and is a day shift. Export licensing review may apply for applicants who are not US citizens or permanent residents.