Digital Design Engineer

About the role

GlobalFoundries is looking for a Digital Design Engineer to develop and verify RTL for digital subsystems within its CPO product, including control logic, register interfaces, link management and DFT structures. The role works closely with architecture, analog/mixed-signal and photonics teams to define digital interfaces for co-packaged optical modules.

Key responsibilities

• Develop, document and maintain RTL (SystemVerilog/Verilog) for digital subsystems, including control logic, register interfaces, link management and DFT structures.
• Collaborate with architecture, analog/mixed-signal and photonics teams to define digital interfaces and control schemes for co-packaged optical modules.
• Own micro-architecture specifications, design reviews and integration of digital IP into the top-level SoC.
• Drive synthesis, timing closure, CDC, lint and low-power (UPF) sign-off with the physical design team.
• Perform FPGA prototyping and testing to validate functionality, accelerate pre-silicon software bring-up and de-risk RTL before tape-out.
• Build reusable verification components, write constrained-random tests and drive functional and code coverage closure.
• Work with the DV team on testbench development, coverage closure and debug.
• Take part in tape-out readiness activities such as ECO planning, gate-level simulation and post-silicon bring-up support.
• Contribute to design methodology, reuse strategy and quality improvements.

Required profile

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field.
• 1+ years of experience in digital RTL design using SystemVerilog/Verilog.
• Solid understanding of synchronous design, CDC, FSMs, pipelining and low-power techniques.
• Hands-on experience with EDA tools (synthesis, lint, CDC, simulation).
• Familiarity with scripting (Python, TCL, Perl) for design automation.
• Strong problem-solving skills and ability to work in a cross-functional team.

Preferred qualifications

• High-speed serial interfaces (SerDes, PCIe, Ethernet, CXL) or optical link control.
• Silicon photonics, co-packaged optics or advanced packaging exposure.
• ARM-based SoC integration, AMBA protocols (AXI/AHB/APB) and standard IP integration flows.
• Prior tape-out experience on advanced process nodes.
• Knowledge of UPF/low-power flows and DFT (scan, MBIST, boundary scan).

What we offer

• Base salary and equity.
• Annual bonus plan.
• Medical insurance.