Emulation Engineer

About the role

Join Cisco's Common ASIC Group to develop advanced emulation environments that accelerate pre‑silicon validation for next‑generation switching systems. You will work with a multidisciplinary team to build, test, and debug high‑speed ASIC prototypes, ensuring reliable silicon for global data connectivity.

Key responsibilities

• Design and maintain emulation infrastructure using C/C++ and TCL.
• Run and refine test plans and traffic scenarios on multi‑terabit ASIC prototypes.
• Collaborate with design, verification, power, and diagnostic teams to identify and resolve performance and functional issues.
• Develop RTL prototypes in Verilog/SystemVerilog for emulation platforms.
• Utilize debug tools such as gdb and waveform viewers to troubleshoot complex hardware.

Required profile

• Master’s degree in Electrical, Electronics, or Computer Engineering with 4+ years of experience, or Bachelor’s degree with 5+ years.
• At least 2 years of hands‑on emulation experience on platforms like Palladium, Veloce, or Zebu.
• Proficiency in RTL development (Verilog/SystemVerilog) and software development (C/C++, TCL).
• Strong analytical and problem‑solving abilities.

Required skills

• C / C++
• TCL
• Verilog / SystemVerilog
• Emulation platforms: Palladium, Veloce, Zebu
• Debug tools: gdb, waveform debuggers
• Scripting: Python, Perl (preferred)
• Knowledge of PCIe, I2C, Ethernet packet headers and protocols