Senior Physical Design Engineer (Floorplan & PnR)

About the role

Envision Employment Solutions is recruiting a Senior Physical Design Engineer (Floorplan & PnR) for a partner IT services and IT consulting company. The engineer owns the implementation side of physical design, from partitioning and power planning through placement, CTS and routing, on advanced technology nodes. The workplace is on site.

Key responsibilities

• Own floorplanning, partitioning, pin assignment and power mesh design at block and full-chip level
• Run placement, CTS, routing and optimisation to close PPA targets
• Drive clock tree planning and analysis, and scan reordering
• Close physical verification: DRC, LVS, antenna and ERC
• Resolve EM/IR issues and contribute to low-power implementation
• Work closely with STA, DFT and RTL teams through to signoff
• Complete multiple design cycles with little supervision

Required profile

• 10+ years of RTL to GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instances
• Tapeout experience; top-level floorplanning is a plus
• Ability to spot congestion in a floorplan before the tool does, and to balance power, performance and area
• Comfortable working independently while keeping the wider team in the loop

Required skills

• Power user of PnR tools from Synopsys and/or Cadence (ICC2, Fusion Compiler, Innovus)
• Excellent floorplan, power plan, CTS, place, route and timing closure skills
• Strong EM/IR, DRC, LVS and ERC analysis and fixing
• Good knowledge of synthesis and DFT scan insertion
• Proficiency in Tcl, Perl, Python and Makefile

To apply, candidates submit their application through Envision Employment Solutions.