Senior Physical Design Engineer (Synthesis, SDC & STA)

About the role

Envision Employment Solutions is recruiting a Senior Physical Design Engineer (Synthesis, SDC & STA) for a partner IT services and IT consulting company. The role owns the front end of the physical design flow on advanced nodes, turning RTL into clean netlists with constraints that hold from synthesis through signoff, and works on-site in New Cairo City.

Key responsibilities

• Own synthesis for complex blocks and full-chip designs on 10nm and below nodes
• Write, review and debug SDC constraints, including partitioning and budgeting from top level to block level
• Drive static timing analysis through to signoff, including SI and noise closure
• Generate and implement functional and timing ECOs
• Develop timing scripts for clock skew analysis, critical path analysis and IO interface timing
• Work with RTL, DFT and PnR teams to close PPA targets
• Support formal verification and low-power implementation

Required profile

• 10+ years of experience in physical design, with deep hands-on work in synthesis, SDC and STA
• Proven RTL-to-GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instances
• Multiple tapeouts with signoff closure

Required skills

• Power user of Synopsys and/or Cadence synthesis and timing tools (Design Compiler, Genus, PrimeTime, Tempus)
• Strong STA/PTSI and signal integrity closure skills
• Good knowledge of DFT scan insertion and its impact on timing
• Proficiency in Tcl, Perl, Python and Makefile