Senior R&D Engineer – Virtual Prototyping

About the role

Synopsys is looking for a Senior Engineer to join its R&D Engineering team, focusing on virtual prototyping and system‑level modeling. You will work on creating scalable SystemC/TLM2.0 models that enable early software development for embedded platforms.

Key responsibilities

• Develop SystemC/TLM2.0 models and C++ components for CPUs, interconnects, memories and peripherals within the Synopsys Virtualizer™ environment.
• Configure and customize Virtualizer platforms to support firmware, bootloader, Linux and RTOS bring‑up.
• Optimize models for performance, scalability and maintainability.
• Integrate virtual platforms with debuggers, build systems and CI pipelines.
• Automate simulation and testing workflows using Python.
• Perform root‑cause analysis across hardware models and software stacks.

Required profile

• Minimum 2 years of professional experience in virtual prototyping, R&D or embedded systems.
• Bachelor’s degree in Communication and Electronics Engineering, Computer Engineering or a related field (GPA ≥ 3.5 or “Very Good with Honors”).
• Fluent English and ability to work with global teams.

Required skills

• Expert‑level C++ (C++11/14/17 or later).
• SystemC with TLM2.0, model composition, timing and synchronization.
• Python for automation, scripting and testing.
• Knowledge of ARM and/or RISC‑V architectures, memory‑mapped I/O and Linux development workflows.
• Experience with Synopsys Virtualizer™ (or similar virtual platform tools) is a plus.