R&D RTL Development Intern

About the role

Join Siemens Digital Industry Software’s R&D team in Cairo as an RTL Development Intern. You will work on real‑world hardware description language (HDL) projects, contributing to the design, implementation, and verification of modular digital components.

Key responsibilities

• Implement modular HDL modules that communicate through predefined interfaces.
• Assist in designing and adding new features and modules.
• Create testbench environments to verify newly implemented modules.
• Participate in debugging and optimization to ensure high‑quality deliverables.
• Stay current with industry trends and best practices in Verilog, SystemVerilog and DPI calls.
• Collaborate with the development team to build and maintain efficient modules.

Required profile

• 3rd or 4th year student in Computer Science, Computer Engineering or Electrical Engineering.
• Solid experience with Verilog and SystemVerilog.
• Strong understanding of digital/RTL design basics.
• Good knowledge of Linux fundamentals.
• Team‑player with strong communication and presentation skills.

Required skills

• Verilog
• SystemVerilog
• Digital RTL design
• Shell scripting
• Perl
• Python
• TCL
• Linux

What we offer

• Mentorship from experienced engineers.
• Hands‑on experience with cutting‑edge PLM software.
• Opportunity to make a direct business impact during a 2‑month summer program.