Digital Verification Development Engineer

About the role

Mixel, a Silvaco company, develops high-performance analog mixed-signal semiconductor IPs used in mobile, display, camera, automotive, VR, AR and AI applications. It is looking for a Digital Verification Development Engineer in Cairo to build and run verification environments for its designs.

Key responsibilities

• Develop test plans from specifications and architect system-level verification environments.
• Develop and maintain UVM-based testbenches for block-level and subsystem-level verification.
• Write constrained-random stimulus, scoreboards, monitors and coverage models in SystemVerilog.
• Contribute to regression infrastructure, continuous integration flows and internal verification methodology.
• Drive functional and code coverage closure, analyse coverage holes and add targeted tests.
• Integrate and configure VIP (Verification IP) for standard protocols.
• Support FPGA-based prototyping and pre-silicon bring-up with validation test suites.
• Execute RTL and gate-level simulations and analyse results.
• Contribute to design and verification process automation.

Required profile

• Bachelor's degree in Electronics or Computer Engineering.
• 0-3 years of experience in the same field.
• 0-3 years of experience developing SV-based verification environments.
• Fluent English.
• Unix/Linux computer skills required.

Required skills

• Strong knowledge of Verilog, SystemVerilog and object-oriented programming languages.
• Strong proficiency in UVM methodology.
• Solid understanding of functional and code coverage metrics and closure.
• Desirable: familiarity with RTL design, synthesis and CDC analysis; working knowledge of shell, Perl and TCL scripting.

What we offer

• Competitive pay, annual and spot bonuses, and long-term incentive plan awards (RSUs).
• Health benefits, paid holidays and time off.
• Learning and leadership opportunities.