Junior Design Layout Engineer

About the role

Join GlobalFoundries' high‑performance Physical Design team to develop next‑generation ultra‑high‑speed circuits for optical engines. As a Junior Design Layout Engineer you will work on state‑of‑the‑art SOI and FinFET technologies, contributing to the physical implementation of analog and mixed‑signal blocks.

Key responsibilities

• Physical implementation of analog and mixed‑signal circuits.
• Floor planning, power planning, placement, and custom routing of ultra‑high‑speed blocks and signals.
• Perform advanced design flows and checks to resolve IR, EM, and crosstalk issues.
• Address ESD and latch‑up constraints.
• Block‑level and top‑level integration efforts.
• Collaborate with front‑end designers to optimize physical designs.
• Participate in design reviews, documentation, and methodology improvements.

Required profile

• Proven track record delivering AMS blocks for production silicon.
• Strong industrial experience in analog/mixed‑signal CMOS layout.
• Experience designing TX, DRVRs, RX, TIAs, and PLLs.
• Experience with chip releases and top‑level ownership.
• Familiarity with SOI or FinFET process technologies (BICMOS a plus).
• Knowledge of scripting languages such as TCL, SKILL, PERL, and SVRF is a plus.

Required skills

• Analog/Mixed‑Signal CMOS layout.
• Layout design of TX, DRVRs, RX, TIAs, PLLs.
• SOI and FinFET process technology.
• Scripting: TCL, SKILL, PERL, SVRF.

What we offer

• Base salary.
• Equity participation.
• Annual bonus plan.
• Medical insurance and comprehensive benefits.